Fab Process Engineering interview prep.

Behavioural questions to expect

1. Walk me through your CV.
2. Tell me about your most impactful process or module project.
3. Tell me about a weakness, a failure, or feedback you've received and worked on.
4. Why fab process engineering — and why this fab vs design or other engineering?
5. Which process module or node would you want to focus on, and why?
6. Why the firm?
7. How would you describe the firm's fabs + process technology in your own words?
8. How does fab process engineering actually drive value for a semiconductor company?

Technical concepts to master

• Lithography + patterning

  EUV vs immersion DUV vs multi-patterning · CD + overlay + EPE · LER / LWR (line-edge / line-width roughness) · Mask + reticle + pellicle · Scanner correctables + APC

• Etch + deposition + CMP

  Etch profile + selectivity + ALE · Microloading + aspect-ratio-dependent etch (ARDE) · ALD conformality + step coverage · CMP dishing + erosion + scratch + slurry · Stress + warpage

• Yield + defectivity + SPC

  Defect Pareto + kill ratio · SPC + control limits + Western Electric rules · Cp / Cpk + process capability · FDC + APC + run-to-run control · Commonality analysis + scrub + KLA / inline FA

• Integration + ramp + qualification

  Integration flow + module owners · NPI + ramp + qualification gates · Copy-exact · DFM + tape-out + first silicon · Tool fleet + chamber matching

Practical drills

• Wafer yield on a leading-edge logic product dropped from 78% to 64% over 4 days on one fab line. Inline defect density on the M2 inspection step doubled. Walk me through your response from containment to root cause to closure, including how you'd use the defect Pareto + kill ratio math to prioritize.
• You're asked to widen the process window of a CMP step on a next-node port — current Cpk on within-wafer non-uniformity is 0.9 (below the 1.33 release gate) and dishing on dense pattern blocks is at spec edge. Design the DOE + qualification plan.
• During NPI ramp of a new product, you see a yield cliff on the M3 layer that only appears at high lot starts. Litho overlay on M3 is at spec, but EPE is wider than qual lots showed. The hypothesis tree points across litho, etch (M2), and CMP (M2). Walk me through how you'd drive resolution.

Smart-question anchors

• Module + scope - which module / tool the role would own in 6-12 months
• Node + product roadmap - current + next node, product mix, recent ramps
• Yield + ramp posture - copy-exact discipline, qual-gate maturity, recent NPI experience
• Tool + vendor partnership - tool stack, vendor MOUs, in-house tooling
• Excursion + SPC culture - excursion-response cadence, SPC / FDC / APC maturity

Sourced from

SEMI + SEMICON + IEDM + VLSI Symposium technical literature · IRDS (International Roadmap for Devices and Systems) + ITRS legacy · AEC / APC + SEMI E10 + SEMI E79 industry standards · Wolf + Tauber / May + Spanos / Plummer + Deal + Griffin - standard semiconductor process textbooks · Glassdoor + Blind + WSO fab-process interview reports + threads