Fab Process Engineering interview prep.

Module / process / integration / yield / equipment engineers at wafer fabs, leading-edge logic foundry, memory fab (DRAM / NAND), mature-node IDM, specialty / analog / power fab.

What interviewers look for

  • Does the candidate own a unit process or module end-to-end, recipe, tool, SPC, excursion response, not just textbook knowledge?
  • Can they chase a yield excursion: Pareto the defect, propose hypotheses, design the experiment, drive root cause, close the loop?
  • Do they reason in SPC + process-window + Cpk terms, not just averages, and respect the variance fab requires?
  • Are they integration-aware: a knob in one module has downstream consequences (etch profile -> overlay, CMP -> defectivity, anneal -> stress)?
  • Can they partner with tool vendors + MFG + EHS + integration + design on a real cleanroom issue, not work in isolation?
  • Do they show the discipline fab demands: 24/7 tool ownership, excursion-paranoid, copy-exact discipline, ramp pressure?

Behavioural questions to expect

  1. Walk me through your CV.

    What it tests: Story coherence + genuine fit for fab process engineering. Teams want evidence of module ownership, SPC discipline, excursion experience, and the 24/7 tool-ownership rhythm fab demands.

  2. Tell me about your most impactful process or module project.

    What it tests: Depth + ownership + SPC discipline. Tests whether the candidate frames problem -> data + hypothesis -> DOE / experiment -> root cause -> sustained outcome, not vague 'I worked on photo'.

  3. Tell me about a weakness, a failure, or feedback you've received and worked on.

    What it tests: Self-awareness + fab discipline. Fab mistakes (missed excursion signal, scrapped lots, missed qual gate, contamination event) carry real wafer cost + ramp cost. Honest call-out + corrective process matters.

  4. Why fab process engineering, and why this fab vs design or other engineering?

    What it tests: Authentic fit for the cleanroom + 24/7 + SPC + excursion-pressure seat. Tests genuine semiconductor processing interest, not someone transitioning because 'chips are hot' or who actually wants chip design.

  5. Which process module or node would you want to focus on, and why?

    What it tests: Specificity + grasp of how sub-specialties differ (litho / etch / deposition / CMP / implant / integration / yield / equipment) AND how leading-edge / mature / memory fabs differ. Generic answers fail.

  6. Why this firm?

    What it tests: Whether the candidate has done the homework on the firm's fabs + nodes + product + process culture, not a name-drop.

  7. How would you describe this firm's fabs + process technology in your own words?

    What it tests: Whether the candidate has internalized HOW the firm makes silicon, fab footprint, node + technology mix, product fit, recent process moves.

  8. How does fab process engineering actually drive value for a semiconductor company?

    What it tests: Whether the candidate understands fab economics: yield + Cpk + ramp speed drive gross margin + capital efficiency; node leadership drives ASP + customer wins; an excursion or yield miss costs millions per day; copy-exact + ramp speed determine when a fab generates revenue.

Technical concepts to master

Lithography + patterning

EUV vs immersion DUV vs multi-patterning
EUV (13.5 nm wavelength) for leading-edge single-exposure patterning; immersion DUV (193 nm + water) historically extended by multi-patterning (LELE / SADP / SAQP) to reach sub-resolution pitches.
CD + overlay + EPE
Critical Dimension = feature size; Overlay = layer-to-layer alignment; Edge Placement Error = combined CD + overlay + LER error at feature edge.
LER / LWR (line-edge / line-width roughness)
Stochastic edge roughness inherent in photoresist exposure; worsens at low photon counts (EUV) due to shot noise.
Mask + reticle + pellicle
Mask = patterned quartz / TaBN; reticle = the mounted mask; pellicle = thin protective film over mask to keep particles out of focal plane.

Etch + deposition + CMP

Etch profile + selectivity + ALE
Profile = sidewall angle + bottom; selectivity = etch rate ratio of target vs mask + underlayer; ALE (atomic layer etch) = self-limiting cyclic etch for sub-nm control.
Microloading + aspect-ratio-dependent etch (ARDE)
Etch rate varies with feature density (microloading) + depth (ARDE, narrower / deeper slows down).
ALD conformality + step coverage
ALD's self-limiting surface chemistry yields near-100% conformality on high-aspect-ratio + 3D structures (FinFET / GAA / 3D NAND).
CMP dishing + erosion + scratch + slurry
Dishing = over-polish into soft material; erosion = pattern density effect; scratch = slurry particle / pad defect; slurry chemistry + pad condition control all three.

Yield + defectivity + SPC

Defect Pareto + kill ratio
Defect Pareto = rank-ordered defect modes by count; kill ratio = fraction of defects that cause die fail; killer defect = high-kill-ratio mode driving yield.
SPC + control limits + Western Electric rules
Statistical Process Control charts (Xbar-R / I-MR) on key metrics; Western Electric rules detect drift / shift / out-of-control patterns before spec violation.
Cp / Cpk + process capability
Cp = spec-width / 6-sigma; Cpk includes centering. Cpk >= 1.33 production acceptable; >= 1.67 strong; tracks process margin.
FDC + APC + run-to-run control
Fault Detection + Classification on tool sensors; Advanced Process Control feedback / feedforward on process responses; tightens variation without manual tuning.

Integration + ramp + qualification

Integration flow + module owners
Full flow = sequence of unit-process modules from FEOL (transistor) through MOL + BEOL (interconnect); each module has an owner; integration owns module-to-module interaction.
NPI + ramp + qualification gates
New Product Introduction = first lots of new product through qualified flow; ramp = scaling volume while improving yield; qualification = gate-by-gate sign-off on recipe + tool + SPC + defectivity.
Copy-exact
Discipline of replicating a qualified process exactly across tools + chambers + fabs, same recipe + same hardware + same procedure, so the second site matches the first without re-development.
DFM + tape-out + first silicon
Design for Manufacturability rules = pattern restrictions the design team must follow so the process yields; tape-out = design hands GDSII to fab; first silicon = initial wafers back validating yield + device.

Practical drills

  • Wafer yield on a leading-edge logic product dropped from 78% to 64% over 4 days on one fab line. Inline defect density on the M2 inspection step doubled. Walk me through your response from containment to root cause to closure, including how you'd use the defect Pareto + kill ratio math to prioritize.
  • You're asked to widen the process window of a CMP step on a next-node port, current Cpk on within-wafer non-uniformity is 0.9 (below the 1.33 release gate) and dishing on dense pattern blocks is at spec edge. Design the DOE + qualification plan.
  • During NPI ramp of a new product, you see a yield cliff on the M3 layer that only appears at high lot starts. Litho overlay on M3 is at spec, but EPE is wider than qual lots showed. The hypothesis tree points across litho, etch (M2), and CMP (M2). Walk me through how you'd drive resolution.

Smart-question anchors

  • Module + scope - which module / tool the role would own in 6-12 months
  • Node + product roadmap - current + next node, product mix, recent ramps
  • Yield + ramp posture - copy-exact discipline, qual-gate maturity, recent NPI experience
  • Tool + vendor partnership - tool stack, vendor MOUs, in-house tooling
  • Excursion + SPC culture - excursion-response cadence, SPC / FDC / APC maturity

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