Walk me through your semiconductor quality + reliability background.

What it tests: Story arc - device-physics / statistics training, JEDEC + AEC-Q exposure, FA + 8D work, customer DPPM programme - because semi quality interviewers need to see physics + statistics + DPPM discipline from the first answer.

Tell me about a quality or reliability programme you've owned.

What it tests: Programme + closed-loop thinking - scope, qualification trail, DPPM outcome - because semi quality is judged on physical root cause + sustained DPPM reduction, not one-shot fixes.

Why semiconductor quality + reliability vs board-level / automotive Tier-1 / A+D quality?

What it tests: Authentic alignment - silicon-physics depth, DPPM scale (parts-per-million on billions of die), customer-fleet thinking - because the physics + statistics + scale delta is the differentiator.

Why this domain - logic / memory / analog / automotive / power / RF?

What it tests: Specificity. Generic answers fail because semi quality varies a lot across domains (advanced-node logic vs automotive AEC-Q vs memory bit-error / soft-error vs power discrete).

What it tests: Real homework - product, qualification posture, recent customer-quality events - not generic name-drop.

What's your read on our product + quality posture?

What it tests: Industry literacy - product mix, market exposure (automotive vs consumer vs data-center), recent quality events.

Tell me what you understand about our quality culture + management system.

What it tests: QMS maturity - IATF 16949 + ISO 9001 + customer-specific overlays, independence of quality function, FA capability, FRACAS-equivalent closed loop.

Walk me through a JEDEC or AEC-Q qualification you owned - plan, execution, escape.

What it tests: Qualification fluency - JESD47 + AEC-Q100 stress test selection, sample size, acceleration model + read-points, failure interpretation, requalification triggers.

Quality Reliability interview prep.

Product / process quality engineers, reliability engineers, yield + quality engineers, JEDEC + AEC-Q qualification engineers, customer-quality / RMA / 8D leads at IDMs, fabless, OSATs, foundries (logic, memory, analog, mixed-signal, power, automotive).

What interviewers look for

Can the candidate apply silicon-physics failure mechanisms (NBTI, HCI, TDDB, EM, soft errors) + acceleration models to set + interpret qualification + field life?
Are they fluent in JEDEC + AEC-Q qualification batteries - HTOL / HAST / TC / ESD / latch-up - and how AEC-Q grades + ISO 26262 ASIL flow down to qual plans?
Can they own ATE + SLT escape analysis - bin pareto, outlier detection, PAT / SBL / DPAT, statistical screens that reduce DPPM without yield bleed?
Do they run 8D + FA closed loops - decap, FIB, SEM, lock-in thermography, OBIRCH / EBIRCH - to physical root cause + sustained corrective action?
Are they fluent in DPPM + FIT math + customer RMA closure - rate calculation, fleet impact, containment + permanent CA + Lessons Learned?
Can they manage QMS overlay - IATF 16949 + VDA 6.3 + PPAP for automotive, JEDEC + customer SOR for general semi - across IDM / fabless / OSAT / foundry boundary?
Are they audit-ready - customer QBR + IATF + ISO surveillance + automotive PPAP + production part approval?

Behavioural questions to expect

Walk me through your semiconductor quality + reliability background.
What it tests: Story arc - device-physics / statistics training, JEDEC + AEC-Q exposure, FA + 8D work, customer DPPM programme - because semi quality interviewers need to see physics + statistics + DPPM discipline from the first answer.
Tell me about a quality or reliability programme you've owned.
What it tests: Programme + closed-loop thinking - scope, qualification trail, DPPM outcome - because semi quality is judged on physical root cause + sustained DPPM reduction, not one-shot fixes.
Why semiconductor quality + reliability vs board-level / automotive Tier-1 / A+D quality?
What it tests: Authentic alignment - silicon-physics depth, DPPM scale (parts-per-million on billions of die), customer-fleet thinking - because the physics + statistics + scale delta is the differentiator.
Why this domain - logic / memory / analog / automotive / power / RF?
What it tests: Specificity. Generic answers fail because semi quality varies a lot across domains (advanced-node logic vs automotive AEC-Q vs memory bit-error / soft-error vs power discrete).
Why this firm?
What it tests: Real homework - product, qualification posture, recent customer-quality events - not generic name-drop.
What's your read on our product + quality posture?
What it tests: Industry literacy - product mix, market exposure (automotive vs consumer vs data-center), recent quality events.
Tell me what you understand about our quality culture + management system.
What it tests: QMS maturity - IATF 16949 + ISO 9001 + customer-specific overlays, independence of quality function, FA capability, FRACAS-equivalent closed loop.
Walk me through a JEDEC or AEC-Q qualification you owned - plan, execution, escape.
What it tests: Qualification fluency - JESD47 + AEC-Q100 stress test selection, sample size, acceleration model + read-points, failure interpretation, requalification triggers.

Technical concepts to master

Silicon-physics failure mechanisms + acceleration

NBTI (Negative Bias Temperature Instability): Vth shift in PMOS under negative gate bias + elevated temperature; causes Vth degradation + speed loss over life.
HCI (Hot Carrier Injection): High-field carriers injected into gate oxide cause Vth + transconductance shift in NMOS; worst at high Vd / low T.
TDDB (Time-Dependent Dielectric Breakdown): Gradual + then catastrophic oxide breakdown under sustained electric field; lifetime drops sharply with Vg.
EM (Electromigration): Metal-ion drift under high current density causes void + extrusion failures in interconnect.

JEDEC + AEC-Q + ISO 26262 + IATF overlay

JEDEC JESD47 + JEP122: JESD47 = consumer / industrial IC qualification stress menu; JEP122 = failure-mechanism + acceleration models.
AEC-Q100 / Q101 / Q200 + grades: Automotive qualification - Q100 IC, Q101 discrete, Q200 passive; Grade 0 (150C) to Grade 3 (85C) maps to under-hood / cabin / infotainment use.
ISO 26262 + ASIL: Functional safety - ASIL A (lowest) to D (highest); drives FMEDA, safety analysis, qualification rigor + diagnostic coverage targets.
IATF 16949 + VDA 6.3 + PPAP: IATF 16949 = automotive QMS; VDA 6.3 = process audit; PPAP / PPA = production part approval flow with customer.

Statistical bin limits + ATE / SLT escape

PAT (Part Average Testing) + DPAT (Dynamic PAT): PAT = reject die outside 6-sigma of lot / wafer mean (per AEC-Q001); DPAT = dynamic per-wafer recalculation; both catch parametric outliers without overkill.
SBL (Statistical Bin Limits) + GDBC (Good Die in Bad Cluster): SBL = wafer-level bin pareto limits flag excursions; GDBC inks out otherwise-good die in spatial clusters of failures.
ATE bin pareto + outlier detection: Final-test bin pareto identifies dominant failure modes; outlier detection flags parts in the tail of normally-distributed parameters.
SLT (System Level Test) + burn-in: SLT = test in a customer-like board / workload to catch escapes ATE misses; burn-in = high-T biased pre-stress to precipitate infant mortality.

FA flow + 8D + DPPM / FIT math

FA flow - electrical, FIB, SEM, lock-in: Electrical characterization (curve trace + ATE re-test) -> fault localization (OBIRCH / EBIRCH / lock-in thermography) -> physical FA (decap + FIB + SEM / TEM) -> root cause.
8D + 5-Why + Ishikawa: 8D = 8-step customer 8D format (D1 team -> D8 closure); 5-Why drills causality; Ishikawa organises causal categories.
DPPM math: DPPM = (defective parts / shipped parts) x 10^6; calculated per failure mode + rolled up per product / customer.
FIT math + chi-square confidence: FIT = failures per 10^9 device-hours; calculated from sample x hours x acceleration factor with chi-square at confidence level.

Practical drills

A new automotive Grade 1 (Tj 125C) logic IC needs to demonstrate <10 FIT at use Tj 90C for the HTOL-stressed wearout mechanisms. HTOL is run at Tj 150C, 1000 hr, 3 lots x 77 parts each (231 total), zero failures. Walk through the acceleration + FIT calc + whether you've passed.
An automotive Tier-1 customer reports 50 DPPM on a Grade 1 microcontroller against a contract of 5 DPPM - 12 field returns in the last quarter, mostly intermittent functional fails after thermal cycling on the customer's ECU. Walk through your engineering + quality response.
A consumer SoC is shipping at 80 DPPM against a 50 DPPM target. The pareto of returns shows 60% of fails are in a single functional bin that escaped final test. Walk through your FA + bin-limit + screen response.

Smart-question anchors

Product + market mix - consumer / industrial / automotive / data-center shaping qualification + DPPM load
Quality function authority - independent of operations + reporting line to chief quality officer
IATF 16949 + automotive customer overlay - PPAP cadence, VDA 6.3 + customer-specific audits
Reliability programme maturity - JEDEC + AEC-Q + ISO 26262 ASIL practice, in-house FA capability
Statistical screen practice - PAT / SBL / DPAT / GDBC deployment, escape rate trend

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