Quality Reliability interview prep.

Behavioural questions to expect

1. Walk me through your semiconductor quality + reliability background.
2. Tell me about a quality or reliability programme you've owned.
3. Why semiconductor quality + reliability vs board-level / automotive Tier-1 / A+D quality?
4. Why this domain - logic / memory / analog / automotive / power / RF?
5. Why the firm?
6. What's your read on our product + quality posture?
7. Tell me what you understand about our quality culture + management system.
8. Walk me through a JEDEC or AEC-Q qualification you owned - plan, execution, escape.

Technical concepts to master

• Silicon-physics failure mechanisms + acceleration

  NBTI (Negative Bias Temperature Instability) · HCI (Hot Carrier Injection) · TDDB (Time-Dependent Dielectric Breakdown) · EM (Electromigration) · Soft errors (SEU / SET)

• JEDEC + AEC-Q + ISO 26262 + IATF overlay

  JEDEC JESD47 + JEP122 · AEC-Q100 / Q101 / Q200 + grades · ISO 26262 + ASIL · IATF 16949 + VDA 6.3 + PPAP · DPPM + FIT contractual targets

• Statistical bin limits + ATE / SLT escape

  PAT (Part Average Testing) + DPAT (Dynamic PAT) · SBL (Statistical Bin Limits) + GDBC (Good Die in Bad Cluster) · ATE bin pareto + outlier detection · SLT (System Level Test) + burn-in · Escape DPPM math + customer correlation

• FA flow + 8D + DPPM / FIT math

  FA flow - electrical, FIB, SEM, lock-in · 8D + 5-Why + Ishikawa · DPPM math · FIT math + chi-square confidence · PPAP + control plan + PFMEA

Practical drills

• A new automotive Grade 1 (Tj 125C) logic IC needs to demonstrate <10 FIT at use Tj 90C for the HTOL-stressed wearout mechanisms. HTOL is run at Tj 150C, 1000 hr, 3 lots x 77 parts each (231 total), zero failures. Walk through the acceleration + FIT calc + whether you've passed.
• An automotive Tier-1 customer reports 50 DPPM on a Grade 1 microcontroller against a contract of 5 DPPM - 12 field returns in the last quarter, mostly intermittent functional fails after thermal cycling on the customer's ECU. Walk through your engineering + quality response.
• A consumer SoC is shipping at 80 DPPM against a 50 DPPM target. The pareto of returns shows 60% of fails are in a single functional bin that escaped final test. Walk through your FA + bin-limit + screen response.

Smart-question anchors

• Product + market mix - consumer / industrial / automotive / data-center shaping qualification + DPPM load
• Quality function authority - independent of operations + reporting line to chief quality officer
• IATF 16949 + automotive customer overlay - PPAP cadence, VDA 6.3 + customer-specific audits
• Reliability programme maturity - JEDEC + AEC-Q + ISO 26262 ASIL practice, in-house FA capability
• Statistical screen practice - PAT / SBL / DPAT / GDBC deployment, escape rate trend

Sourced from

JEDEC JESD47 + JESD22 + JEP122 + JESD78 standards · AEC-Q100 / Q101 / Q200 automotive qualification + AEC-Q001 PAT · ISO 26262 + IATF 16949 + VDA 6.3 automotive QMS + functional safety · JEDEC JEP148 + JESD89 soft-error rate standards · ANSI / ASQ Z1.4 + Z1.9 + AIAG PPAP + FMEA + MSA reference manuals · Glassdoor + Blind + industry reliability conference (IRPS / IEDM) interview reports